electrical engineering exercise and need the explanation and answer to help me learn.
hello i need help with my lab for – Microcontrollers and please use the program Code Composer Studio and i attached the lab down below thank you for your help}See Table Register, optionally shifted by constantA comma-separated list of registers, enclosed in braces { and }.See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2.As , must not include the PC.See Table PSR fields.As , including the PC.APSR (Application Program Status Register), CPSR (Current Processor Status Register), or SPSR (Saved Processor Status Register)Either nzcvq (ALU flags PSR[31:27]) or g (SIMD GE flags PSR[19:16])C*, V*Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later.§See Table ARM architecture versions.Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those+/-+ or –. (+ may be omitted.)shown in Table Register, optionally shifted by constant.Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).x,yB meaning half-register [15:0], or T meaning [31:16].See Table Processor ModesARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.SPmSP for the processor mode specified by Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bitLeast significant bit of bitfield.pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00.Width of bitfield. + must be <= 32.See Table Prefixes for Parallel instructions{X}RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.{IA|IB|DA|DB}Increment After, Increment Before, Decrement After, or Decrement Before. {!}Updates base register after data transfer if ! present (pre-indexed).IB and DA are not available in Thumb state. If omitted, defaults to IA.{S}Updates condition flags if S present.B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively.{T}User mode privilege if T present.SB and SH are not available in STR instructions.{R}Rounds result to nearest if R present, otherwise truncates result.Operation§AssemblerS updatesActionNotesAddAddADD{S} Rd, Rn, NZCVRd := Rn + Operand2Nwith carryADC{S} Rd, Rn, NZCVRd := Rn + Operand2 + CarryNwideT2ADD Rd, Rn, #Rd := Rn + imm12, imm12 range 0-4095T, Psaturating {doubled}5EQ{D}ADD Rd, Rm, RnRd := SAT(Rm + Rn) doubled: Rd := SAT(Rm + SAT(Rn * 2))QAddressForm PC-relative addressADR Rd, Rd := , for range from current instruction see Note LN, LSubtractSubtractSUB{S} Rd, Rn, NZCVRd := Rn – Operand2Nwith carrySBC{S} Rd, Rn, NZCVRd := Rn – Operand2 – NOT(Carry)NwideT2SUB Rd, Rn, #Rd := Rn – imm12, imm12 range 0-4095T, Preverse subtractRSB{S} Rd, Rn, NZCVRd := Operand2 – RnNreverse subtract with carryRSC{S} Rd, Rn, NZCVRd := Operand2 – Rn – NOT(Carry)Asaturating {doubled}5EQ{D}SUB Rd, Rm, RnRd := SAT(Rm – Rn)doubled: Rd := SAT(Rm – SAT(Rn * 2))QException return without stackSUBS PC, LR, #NZCVPC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255.ParallelarithmeticHalfword-wise addition6ADD16 Rd, Rn, RmRd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0]GHalfword-wise subtraction6SUB16 Rd, Rn, RmRd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0]GByte-wise addition6ADD8 Rd, Rn, RmRd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]GByte-wise subtraction6SUB8 Rd, Rn, RmRd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]GHalfword-wise exchange, add, subtract6ASX Rd, Rn, RmRd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16]GHalfword-wise exchange, subtract, add6SAX Rd, Rn, RmRd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16]GUnsigned sum of absolute differences6USAD8 Rd, Rm, RsRd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])and accumulate6USADA8 Rd, Rm, Rs, RnRd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])SaturateSigned saturate word, right shift6SSAT Rd, #, Rm{, ASR }Rd := SignedSat((Rm ASR sh), sat). range 1-32, range 1-31.Q, RSigned saturate word, left shift6SSAT Rd, #, Rm{, LSL }Rd := SignedSat((Rm LSL sh), sat). range 1-32, range 0-31.QSigned saturate two halfwords6SSAT16 Rd, #, RmRd[31:16] := SignedSat(Rm[31:16], sat),Rd[15:0] := SignedSat(Rm[15:0], sat). range 1-16.QUnsigned saturate word, right shift6USAT Rd, #, Rm{, ASR }Rd := UnsignedSat((Rm ASR sh), sat). range 0-31, range 1-31.Q, RUnsigned saturate word, left shift6USAT Rd, #, Rm{, LSL }Rd := UnsignedSat((Rm LSL sh), sat). range 0-31, range 0-31.QUnsigned saturate two halfwords6USAT16 Rd, #, RmRd[31:16] := UnsignedSat(Rm[31:16], sat),Rd[15:0] := UnsignedSat(Rm[15:0], sat). range 0-15.Q Rd, Rn, RmRd := Rn / Rm is SDIV (signed) or UDIV (unsigned)TMovedataMoveMOV{S} Rd, NZCRd := Operand2See also Shift instructionsNnotMVN{S} Rd, NZCRd := 0xFFFFFFFF EOR Operand2NtopT2MOVT Rd, #Rd[31:16] := imm16, Rd[15:0] unaffected, imm16 range 0-65535wideT2MOV Rd, #Rd[15:0] := imm16, Rd[31:16] = 0, imm16 range 0-6553540-bit accumulator to registerXSMRA RdLo, RdHi, AcRdLo := Ac[31:0], RdHi := Ac[39:32]register to 40-bit accumulatorXSMAR Ac, RdLo, RdHiAc[31:0] := RdLo, Ac[39:32]:= RdHi[7:0]ShiftArithmetic shift rightASR{S} Rd, Rm, NZCRd := ASR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, ASR NLogical shift leftLSL{S} Rd, Rm, NZCRd := LSL(Rm, Rs|sh)Same as MOV{S} Rd, Rm, LSL NLogical shift rightLSR{S} Rd, Rm, NZCRd := LSR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, LSR NRotate rightROR{S} Rd, Rm, NZCRd := ROR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, ROR NRotate right with extendRRX{S} Rd, RmNZCRd := RRX(Rm)Same as MOV{S} Rd, Rm, RRXCount leading zeros5CLZ Rd, RmRd := number of leading zeros in RmCompareCompareCMP Rn, NZCVUpdate CPSR flags on Rn – Operand2NnegativeCMN Rn, NZCVUpdate CPSR flags on Rn + Operand2NLogicalTestTST Rn, NZCUpdate CPSR flags on Rn AND Operand2NTest equivalenceTEQ Rn, NZCUpdate CPSR flags on Rn EOR Operand2ANDAND{S} Rd, Rn, NZCRd := Rn AND Operand2NEOREOR{S} Rd, Rn, NZCRd := Rn EOR Operand2NORRORR{S} Rd, Rn, NZCRd := Rn OR Operand2NORNT2ORN{S} Rd, Rn, NZCRd := Rn OR NOT Operand2TBit ClearBIC{S} Rd, Rn, NZCRd := Rn AND NOT Operand2N, #Rd[(width+lsb–1):lsb] := 0, other bits of Rd unaffectedBit Field InsertT2BFI Rd, Rn, #, #Rd[(width+lsb–1):lsb] := Rn[(width-1):0], other bits of Rd unaffectedSigned Bit Field ExtractT2SBFX Rd, Rn, #, #Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( Rn[width+lsb–1] )Unsigned Bit Field ExtractT2UBFX Rd, Rn, #, #Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( 0 )PackPack halfword bottom + top6PKHBT Rd, Rn, Rm{, LSL #}Rd[15:0] := Rn[15:0], Rd[31:16] := (Rm LSL sh)[31:16]. sh 0-31.Pack halfword top + bottom6PKHTB Rd, Rn, Rm{, ASR #}Rd[31:16] := Rn[31:16], Rd[15:0] := (Rm ASR sh)[15:0]. sh 1-32.SignedextendHalfword to word6SXTH Rd, Rm{, ROR #}Rd[31:0] := SignExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.NTwo bytes to halfwords6SXTB16 Rd, Rm{, ROR #}Rd[31:16] := SignExtend((Rm ROR (8 * sh))[23:16]),Rd[15:0] := SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.Byte to word6SXTB Rd, Rm{, ROR #}Rd[31:0] := SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.NUnsignedextendHalfword to word6UXTH Rd, Rm{, ROR #}Rd[31:0] := ZeroExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.NTwo bytes to halfwords6UXTB16 Rd, Rm{, ROR #}Rd[31:16] := ZeroExtend((Rm ROR (8 * sh))[23:16]),Rd[15:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.Byte to word6UXTB Rd, Rm{, ROR #}Rd[31:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.NSignedextendwith addHalfword to word, add6SXTAH Rd, Rn, Rm{, ROR #}Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.Two bytes to halfwords, add6SXTAB16 Rd, Rn, Rm{, ROR #}Rd[31:16] := Rn[31:16] + SignExtend((Rm ROR (8 * sh))[23:16]),Rd[15:0] := Rn[15:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.Byte to word, add6SXTAB Rd, Rn, Rm{, ROR #}Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.Unsignedextendwith addHalfword to word, add6UXTAH Rd, Rn, Rm{, ROR #}Rd[31:0] := Rn[31:0] + ZeroExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.Two bytes to halfwords, add6UXTAB16 Rd, Rn, Rm{, ROR #}Rd[31:16] := Rn[31:16] + ZeroExtend((Rm ROR (8 * sh))[23:16]),Rd[15:0] := Rn[15:0] + ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.Byte to word, add6UXTAB Rd, Rn, Rm{, ROR #}Rd[31:0] := Rn[31:0] + ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.ReverseBits in wordT2RBIT Rd, RmFor (i = 0; i < 32; i++) : Rd[i] = Rm[31– i]Bytes in word6REV Rd, RmRd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24]NBytes in both halfwords6REV16 Rd, RmRd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:24]NBytes in low halfword,sign extend6REVSH Rd, RmRd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFFNSelectSelect bytes6SEL Rd, Rn, RmRd[7:0] := Rn[7:0] if GE[0] = 1, else Rd[7:0] := Rm[7:0]Bits[15:8], [23:16], [31:24] selected similarly by GE[1], GE[2], GE[3]If-ThenIf-ThenT2IT{pattern} {cond}Makes up to four following instructions conditional, according to pattern. pattern is a string of up to three letters. Each letter can be T (Then) or E (Else).The first instruction after IT has condition cond. The following instructions have condition cond if the corresponding letter is T, or the inverse of cond if the corresponding letter is E.See Table Condition Field for available condition codes.T, UBranchBranchB PC := label. label is this instruction ±32MB (T2: ±16MB, T: –252 – +256B)N, Bwith linkBL LR := address of next instruction, PC := label. label is this instruction ±32MB (T2: ±16MB).and exchange4TBX RmPC := Rm. Target is Thumb if Rm[0] is 1, ARM if Rm[0] is 0.Nwith link and exchange (1)5TBLX LR := address of next instruction, PC := label, Change instruction set.label is this instruction ±32MB (T2: ±16MB).Cwith link and exchange (2)5BLX RmLR := address of next instruction, PC := Rm[31:1]. Change to Thumb if Rm[0] is 1, to ARM if Rm[0] is 0.Nand change to Jazelle state5JBXJ RmChange to Jazelle state if availableCompare, branch if (non) zeroT2CB{N}Z Rn,If Rn {== or !=} 0 then PC := label. label is (this instruction + 4-130).N,T,UTable Branch ByteT2TBB [Rn, Rm]PC = PC + ZeroExtend( Memory( Rn + Rm, 1) << 1). Branch range 4-512. Rn can be PC.T, UTable Branch HalfwordT2TBH [Rn, Rm, LSL #1]PC = PC + ZeroExtend( Memory( Rn + Rm << 1, 2) << 1). Branch range 4-131072. Rn can be PC.T, UMove to or from PSRPSR to registerMRS Rd, Rd := PSRregister flags to APSR flagsMSR APSR_, RmAPSR_ := Rmimmediate flags to APSR flagsMSR APSR_, #APSR_ := immed_8rregister to PSRMSR _, RmPSR := Rm (selected bytes only)immediate to PSRMSR _, #PSR := immed_8r (selected bytes only)ProcessorstatechangeChange processor state6CPSID {, #}Disable specified interrupts, optional change mode.U, N6CPSIE {, #}Enable specified interrupts, optional change mode.U, NChange processor mode6CPS #USet endianness6SETEND Sets endianness for loads and stores. can be BE (Big Endian) or LE (Little Endian).U, N is LDRAction if is STRNotesLoador storeword, byteor halfwordImmediate offset{size}{T} Rd, [Rn {, #}]{!}Rd := [address, size][address, size] := Rd1, NPost-indexed, immediate{size}{T} Rd, [Rn], #Rd := [address, size][address, size] := Rd2Register offset{size} Rd, [Rn, +/-Rm {, }]{!}Rd := [address, size][address, size] := Rd3, NPost-indexed, register{size}{T} Rd, [Rn], +/-Rm {, }Rd := [address, size][address, size] := Rd4PC-relative{size} Rd, Rd := [label, size]Not available5, NLoad or storedoublewordImmediate offset5ED Rd1, Rd2, [Rn {, #}]{!}Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd26, 9Post-indexed, immediate5ED Rd1, Rd2, [Rn], #Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd26, 9Register offset5ED Rd1, Rd2, [Rn, +/-Rm {, }]{!}Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd27, 9Post-indexed, register5ED Rd1, Rd2, [Rn], +/-Rm {, }Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd27, 9PC-relative5ED Rd1, Rd2, Rd1 := [label], Rd2 := [label + 4]Not available8, 9Preload data or instruction§(PLD)§(PLI)§(PLDW)AssemblerAction if is PLDAction if is PLIAction if is PLDWNotesImmediate offset5E77MP [Rn {, #}]Preload [address, 32] (data)Preload [address, 32] (instruction)Preload to Write [address, 32] (data)1, CRegister offset5E77MP [Rn, +/-Rm {, }]Preload [address, 32] (data)Preload [address, 32] (instruction)Preload to Write [address, 32] (data)3, CPC-relative5E7 Preload [label, 32] (data)Preload [label, 32] (instruction)5, COther memory operations§AssemblerActionNotesLoad multipleBlock data loadLDM{IA|IB|DA|DB} Rn{!}, Load list of registers from [Rn]N, Ireturn (and exchange)LDM{IA|IB|DA|DB} Rn{!}, Load registers, PC := [address][31:1] (§ 5T: Change to Thumb if [address][0] is 1)Iand restore CPSRLDM{IA|IB|DA|DB} Rn{!}, ^Load registers, branch (§ 5T: and exchange), CPSR := SPSR. Exception modes only.IUser mode registersLDM{IA|IB|DA|DB} Rn, ^Load list of User mode registers from [Rn]. Privileged modes only.IPopPOP Canonical form of LDM SP!, NLoadexclusiveSemaphore operation6LDREX Rd, [Rn]Rd := [Rn], tag address as exclusive access. Outstanding tag set if not shared address.Rd, Rn not PC.Halfword or Byte6KLDREX{H|B} Rd, [Rn]Rd[15:0] := [Rn] or Rd[7:0] := [Rn], tag address as exclusive access. Outstanding tag set if not shared address. Rd, Rn not PC.Doubleword6KLDREXD Rd1, Rd2, [Rn]Rd1 := [Rn], Rd2 := [Rn+4], tag addresses as exclusive accessOutstanding tags set if not shared addresses. Rd1, Rd2, Rn not PC.9Store multiplePush, or Block data storeSTM{IA|IB|DA|DB} Rn{!}, Store list of registers to [Rn]N, IUser mode registersSTM{IA|IB|DA|DB} Rn{!}, ^Store list of User mode registers to [Rn]. Privileged modes only.IPushPUSH Canonical form of STMDB SP!, NStoreexclusiveSemaphore operation6STREX Rd, Rm, [Rn]If allowed, [Rn] := Rm, clear exclusive tag, Rd := 0. Else Rd := 1. Rd, Rm, Rn not PC.Halfword or Byte6KSTREX{H|B} Rd, Rm, [Rn]If allowed, [Rn] := Rm[15:0] or [Rn] := Rm[7:0], clear exclusive tag, Rd := 0. Else Rd := 1Rd, Rm, Rn not PC.Doubleword6KSTREXD Rd, Rm1, Rm2, [Rn]If allowed, [Rn] := Rm1, [Rn+4] := Rm2, clear exclusive tags, Rd := 0. Else Rd := 1Rd, Rm1, Rm2, Rn not PC.10Clear exclusive6KCLREXClear local processor exclusive tagCNotes: availability and range of options for Load, Store, and Preload operationsNoteARM Word, B, DARM SB, H, SHARM T, BTThumb-2 Word, B, SB, H, SH, DThumb-2 T, BT, SBT, HT, SHT1offset: – 4095 to +4095offset: –255 to +255Not availableoffset: –255 to +255 if writeback, –255 to +4095 otherwiseoffset: 0 to +255, writeback not allowed2offset: – 4095 to +4095offset: –255 to +255offset: – 4095 to +4095offset: –255 to +255Not available3Full range of {, }{, } not allowedNot available restricted to LSL #, range 0 to 3Not available4Full range of {, }{, } not allowedFull range of {, }Not availableNot available5label within +/– 4092 of current instructionNot availableNot availablelabel within +/– 4092 of current instructionNot available6offset: –255 to +255–offset: –1020 to +1020, must be multiple of 4.-7{, } not allowed–Not available-8label within +/– 252 of current instruction–Not available-9Rd1 even, and not r14, Rd2 == Rd1 + 1.–Rd1 != PC, Rd2 != PC-10Rm1 even, and not r14, Rm2 == Rm1 + 1.–Rm1 != PC, Rm2 != PC-, , CRd, CRn, CRm{, }Coprocessor definedC2Move to ARM register from coprocessorMRC{2} , , Rd, CRn, CRm{, }Coprocessor definedC2Two ARM register move5EMRRC , , Rd, Rn, CRmCoprocessor definedAlternative two ARM register move6MRRC2 , , Rd, Rn, CRmCoprocessor definedCMove to coproc from ARM regMCR{2} , , Rd, CRn, CRm{, }Coprocessor definedC2Two ARM register move5EMCRR , , Rd, Rn, CRmCoprocessor definedAlternative two ARM register move6MCRR2 , , Rd, Rn, CRmCoprocessor definedCLoads and stores, pre-indexed{2} , CRd, [Rn, #+/-]{!}op: LDC or STC. offset: multiple of 4 in range 0 to 1020.Coprocessor definedC2Loads and stores, zero offset{2} , CRd, [Rn] {, 8-bit copro. option}op: LDC or STC.Coprocessor definedC2Loads and stores, post-indexed{2} , CRd, [Rn], #+/-op: LDC or STC. offset: multiple of 4 in range 0 to 1020.Coprocessor definedC2Miscellaneous operations§AssemblerActionNotesSwap wordSWP Rd, Rm, [Rn]temp := [Rn], [Rn] := Rm, Rd := temp.A, DSwap byteSWPB Rd, Rm, [Rn]temp := ZeroExtend([Rn][7:0]), [Rn][7:0] := Rm[7:0], Rd := tempA, DStore return state6SRS{IA|IB|DA|DB} SP{!}, #[SPm] := LR, [SPm + 4] := CPSRC, IReturn from exception6RFE{IA|IB|DA|DB} Rn{!}PC := [Rn], CPSR := [Rn + 4]C, IBreakpoint5BKPT Prefetch abort or enter debug state. 16-bit bitfield encoded in instruction.C, NSecure Monitor CallZSMC Secure Monitor Call exception. 4-bit bitfield encoded in instruction. Formerly SMI.Supervisor CallSVC Supervisor Call exception. 24-bit bitfield encoded in instruction. Formerly SWI.NNo operation6KNOPNone, might not even consume any time.N, VHintsDebug Hint7DBGProvide hint to debug and related systems.Data Memory Barrier7DMBEnsure the order of observation of memory accesses.CData Synchronization Barrier7DSBEnsure the completion of memory accesses,CInstruction Synchronization Barrier7ISBFlush processor pipeline and branch prediction logic.CSet event6KSEVSignal event in multiprocessor system. NOP if not implemented.NWait for event6KWFEWait for event, IRQ, FIQ, Imprecise abort, or Debug entry request. NOP if not implemented.NWait for interrupt6KWFIWait for IRQ, FIQ, Imprecise abort, or Debug entry request. NOP if not implemented.NYield6KYIELDYield control to alternative thread. NOP if not implemented.NNotesANot available in Thumb state.PRn can be the PC in Thumb state in this instruction.BCan be conditional in Thumb state without having to be in an IT block.QSets the Q flag if saturation (addition or substraction) or overflow (multiplication) occurs. Read and reset the Q flag using MRS and MSR.CCondition codes are not allowed in ARM state.R range is 1-32 in the ARM instruction.C2The optional 2 is available from ARMv5. It provides an alternative operation. Condition codes are not allowed for the alternative form in ARM state.SThe S modifier is not available in the Thumb-2 instruction.DDeprecated. Use LDREX and STREX instead.TNot available in ARM state.GUpdates the four GE flags in the CPSR based on the results of the individual operations.UNot allowed in an IT block. Condition codes not allowed in either ARM or Thumb state.IIA is the default, and is normally omitted.VThe assembler inserts a suitable instruction if the NOP instruction is not available.LARM: . 16-bit Thumb: multiple of 4 in range 0-1020. 32-bit Thumb: 0-4095.NSome or all forms of this instruction are 16-bit (Narrow) instructions in Thumb-2 code. For details see the Thumb 16-bit Instruction Set (UAL) Quick Reference Card.GESigned greater than or equalGreater than or equalRegister, optionally shifted by constant (see below)Rm {, }LTSigned less thanLess than, or unorderedRegister, logical shift left by registerRm, LSL RsGTSigned greater thanGreater thanRegister, logical shift right by registerRm, LSR RsLESigned less than or equalLess than or equal, or unorderedRegister, arithmetic shift right by registerRm, ASR RsALAlways (normally omitted)Always (normally omitted)Register, rotate right by registerRm, ROR RsAll ARM instructions (except those with Note C or Note U) can have any one of these condition codes after the instruction mnemonic (that is, before the first space in the instruction as shown on this card). This condition is encoded in the instruction.All Thumb-2 instructions (except those with Note U) can have any one of these condition codes after the instruction mnemonic. This condition is encoded in a preceding IT instruction (except in the case of conditional Branch instructions). Condition codes in instructions must match those in the preceding IT instruction.On processors without Thumb-2, the only Thumb instruction that can have a condition code is B .Register, optionally shifted by constant(No shift)RmSame as Rm, LSL #0Logical shift leftRm, LSL #Allowed shifts 0-31Logical shift rightRm, LSR #Allowed shifts 1-32Arithmetic shift rightRm, ASR #Allowed shifts 1-32Rotate rightRm, ROR #Allowed shifts 1-31Rotate right with extendRm, RRXProcessor ModesPrefixes for Parallel Instructions16UserSSigned arithmetic modulo 28 or 216, sets CPSR GE bitsPSR fields(use at least one suffix)17FIQ Fast InterruptQSigned saturating arithmeticSuffixMeaning18IRQ InterruptSHSigned arithmetic, halving resultscControl field mask bytePSR[7:0]19SupervisorUUnsigned arithmetic modulo 28 or 216, sets CPSR GE bitsfFlags field mask bytePSR[31:24]23AbortUQUnsigned saturating arithmeticsStatus field mask bytePSR[23:16]27UndefinedUHUnsigned arithmetic, halving resultsxExtension field mask bytePSR[15:8]31SystemProprietary NoticeWords and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.This reference card is intended only to assist the reader in the use of the product. ARM Ltd shallnot be liable for any loss or damage arising from the use of any information in this reference card, or any error or omission in such information, or any incorrect use of the product.Document NumberARM QRC 0001MChange LogIssueDateChangeIssueDateChangeAJune 1995First ReleaseBSept 1996Second ReleaseCNov 1998Third ReleaseDOct 1999Fourth ReleaseEOct 2000Fifth ReleaseFSept 2001Sixth ReleaseGJan 2003Seventh ReleaseHOct 2003Eighth ReleaseIDec 2004Ninth ReleaseJMay 2005RVCT 2.2 SP1KMarch 2006RVCT 3.0LMarch 2007RVCT 3.1MSept 2008RVCT 4.0
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